Systems and methods for flyback power converters with switching frequency and peak current adjustments

ABSTRACT

System and method for regulating a power converter. The system includes a comparator configured to receive a first signal and a second signal and generate a comparison signal based on at least information associated with the first signal and the second signal. The first signal is associated with at least an output current of a power converter. Additionally, the system includes a pulse-width-modulation generator configured to receive at least the comparison signal and generate a modulation signal based on at least information associated with the comparison signal, and a driver component configured to receive the modulation signal and output a drive signal to a switch to adjust a primary current flowing through a primary winding of the power converter. The modulation signal is associated with a modulation frequency corresponding to a modulation period.

1. CROSS-REFERENCES TO RELATED APPLICATIONS

This application is a continuation of U.S. patent application Ser. No. 14/293,280, filed Jun. 2, 2014, which is a continuation of U.S. patent application Ser. No. 13/164,608, filed Jun. 20, 2011, which claims priority to Chinese Patent Application No. 201110144768.2, filed May 23, 2011, all of these applications being incorporated by reference herein for all purposes.

Additionally, U.S. patent application Ser. Nos. 12/859,138 and 13/052,869 are incorporated by reference herein for all purposes.

2. BACKGROUND OF THE INVENTION

The present invention is directed to integrated circuits. More particularly, the invention provides switching frequency and peak current adjustments in response to loading changes. Merely by way of example, the invention has been applied to a flyback power converter. But it would be recognized that the invention has a much broader range of applicability.

Generally, a conventional power conversion system often uses a transformer to isolate the input voltage on the primary side and the output voltage on the secondary side. To regulate the output voltage, certain components, such as TL431 and an opto-coupler, can be used to transmit a feedback signal from the secondary side to a controller chip on the primary side. Alternatively, the output voltage on the secondary side can be imaged to the primary side, so the output voltage is controlled by directly adjusting some parameters on the primary side.

FIG. 1 is a simplified diagram showing a conventional flyback power conversion system with primary-side sensing and regulation. The power conversion system 100 includes a primary winding 110, a secondary winding 112, an auxiliary winding 114, a power switch 120, a current sensing resistor 130, an equivalent resistor 140 for an output cable, resistors 150 and 152, and a rectifying diode 160. For example, the power switch 120 is a bipolar transistor. In another example, the power switch 120 is a MOS transistor.

To regulate the output voltage within a predetermined range, information related to the output voltage and the output loading often needs to be extracted. In the power conversion system 100, such information can be extracted through the auxiliary winding 114. When the power switch 120 is turned on, the energy is stored in the secondary winding 112. Then, when the power switch 120 is turned off, the stored energy is released to the output terminal, and the voltage of the auxiliary winding 114 maps the output voltage on the secondary side as shown below.

$\begin{matrix} {V_{FB} = {{\frac{R_{2}}{R_{1} + R_{2}} \times V_{aux}} = {k \times n \times \left( {V_{o} + V_{F} + {I_{o} \times R_{eq}}} \right)}}} & \left( {{Equation}\mspace{14mu} 1} \right) \end{matrix}$

where V_(FB) represents a voltage at a node 154, and V_(aux) represents the voltage of the auxiliary winding 114. R₁ and R₂ represent the resistance values of the resistors 150 and 152 respectively. Additionally, n represents a turns ratio between the auxiliary winding 114 and the secondary winding 112. Specifically, n is equal to the number of turns of the auxiliary winding 114 divided by the number of turns of the secondary winding 112. V_(o) and I_(o) represent the output voltage and the output current respectively. Moreover, V_(F) represents the forward voltage of the rectifying diode 160, and R_(eq) represents the resistance value of the equivalent resistor 140. Also, k represents a feedback coefficient as shown below:

$\begin{matrix} {k = \frac{R_{2}}{R_{1} + R_{2}}} & \left( {{Equation}\mspace{14mu} 2} \right) \end{matrix}$

FIG. 2 is a simplified diagram showing a conventional operation mechanism for the flyback power conversion system 100. As shown in FIG. 2, the controller chip of the conversion system 100 uses a sample-and-hold mechanism. When the demagnetization process on the secondary side is almost completed and the current I_(sec) of the secondary winding 112 almost becomes zero, the voltage V_(aux) of the auxiliary winding 112 is sampled at, for example, point A of FIG. 2. The sampled voltage value is usually held until the next voltage sampling is performed. Through a negative feedback loop, the sampled voltage value can become equal to a reference voltage V_(ref). Therefore,

V _(FB) =V _(ref)  (Equation 3)

Combining Equations 1 and 3, the following can be obtained:

$\begin{matrix} {V_{o} = {\frac{V_{ref}}{k \times n} - V_{F} - {I_{o} \times R_{eq}}}} & \left( {{Equation}\mspace{14mu} 4} \right) \end{matrix}$

Based on Equation 4, the output voltage decreases with the increasing output current.

But the power conversion system 100 often cannot provide effective response to output loading changes. Hence it is highly desirable to improve the techniques of primary-side sensing and regulation.

3. BRIEF SUMMARY OF THE INVENTION

The present invention is directed to integrated circuits. More particularly, the invention provides switching frequency and peak current adjustments in response to loading changes. Merely by way of example, the invention has been applied to a flyback power converter. But it would be recognized that the invention has a much broader range of applicability.

According to one embodiment, a system for regulating a power converter includes a comparator configured to receive a first signal and a second signal and generate a comparison signal based on at least information associated with the first signal and the second signal. The first signal is associated with at least an output current of a power converter. Additionally, the system includes a pulse-width-modulation generator configured to receive at least the comparison signal and generate a modulation signal based on at least information associated with the comparison signal, and a driver component configured to receive the modulation signal and output a drive signal to a switch to adjust a primary current flowing through a primary winding of the power converter. The modulation signal is associated with a modulation frequency corresponding to a modulation period. The modulation frequency increases with the output current at a first slope within a first current range, the modulation frequency increases with the output current at a second slope within a second current range, and the modulation frequency increases with the output current at a third slope within a third current range. The first current range and the third current range are separated by at least the second current range, and each of the first slope, the second slope, and the third slope is larger than zero. The primary current is associated with a peak magnitude for each modulation period. The peak magnitude remains constant or increases with respect to the output current at a fourth slope within a fourth current range, and the fourth slope is equal to or larger than zero. The peak magnitude increases with the output current at a fifth slope within a fifth current range, and the fifth slope is larger than zero. The peak magnitude remains constant or increases with respect to the output current at a sixth slope within a sixth current range, and the sixth slope is equal to or larger than zero. The fourth current range and the sixth current range are separated by at least the fifth current range.

According to another embodiment, a method for regulating a power converter includes receiving a first signal and a second signal. The first signal is associated with at least an output current of a power converter. Additionally, the method includes processing information associated with the first signal and the second signal, generating a comparison signal based on at least information associated with the first signal and the second signal, receiving at least the comparison signal, and generating a modulation signal based on at least information associated with the comparison signal. Moreover, the method includes receiving the modulation signal, and outputting a drive signal based on at least at least information associated with the modulation signal to adjust a primary current flowing through a primary winding of the power converter. The modulation signal is associated with a modulation frequency corresponding to a modulation period. The modulation frequency increases with the output current at a first slope within a first current range, the modulation frequency increases with the output current at a second slope within a second current range, and the modulation frequency increases with the output current at a third slope within a third current range. The first current range and the third current range are separated by at least the second current range, and each of the first slope, the second slope, and the third slope is larger than zero. The primary current is associated with a peak magnitude for each modulation period. The peak magnitude remains constant or increases with respect to the output current at a fourth slope within a fourth current range, and the fourth slope is equal to or larger than zero. The peak magnitude increases with the output current at a fifth slope within a fifth current range, and the fifth slope is larger than zero. The peak magnitude remains constant or increases with respect to the output current at a sixth slope within a sixth current range, and the sixth slope is equal to or larger than zero. The fourth current range and the sixth current range are separated by at least the fifth current range.

According to yet another embodiment, a system for regulating a power converter includes a first comparator configured to receive a first signal and a second signal and generate a first comparison signal based on at least information associated with the first signal and the second signal. The first signal is associated with at least an output current of a power converter. Additionally, the system includes a second comparator configured to receive a third signal and a fourth signal and generate a second comparison signal based on at least information associated with the third signal and the fourth signal. The third signal is related to the second signal, and the fourth signal is associated with a primary current flowing through a primary winding of the power converter. Moreover, the system includes a logic component configured to receive at least the second comparison signal and generate a logic signal based on at least information associated with the second comparison signal, a pulse-width-modulation generator configured to receive at least the first comparison signal and the logic signal and generate a modulation signal based on at least information associated with the first comparison signal and the logic signal, and a driver component configured to receive the modulation signal and output a drive signal to a switch to adjust the primary current.

According to yet another embodiment, a method for regulating a power converter includes receiving a first signal and a second signal, and the first signal is associated with at least an output current of a power converter. Additionally, the method includes processing information associated with the first signal and the second signal, generating a first comparison signal based on at least information associated with the first signal and the second signal, and receiving a third signal and a fourth signal, the third signal being related to the second signal. The fourth signal is associated with a primary current flowing through a primary winding of the power converter. Moreover, the method includes processing information associated with the third signal and the fourth signal, generating a second comparison signal based on at least information associated with the third signal and the fourth signal, receiving at least the second comparison signal, processing information associated with the second comparison signal, and generating a logic signal based on at least information associated with the second comparison signal. Also, the method includes receiving at least the first comparison signal and the logic signal, generating a modulation signal based on at least information associated with the first comparison signal and the logic signal, receiving the modulation signal, and outputting a drive signal based on at least information associated with the modulation signal to adjust the primary current.

According to yet another embodiment, a system for regulating a power converter includes a first comparator configured to receive a first signal and a second signal and generate a first comparison signal based on at least information associated with the first signal and the second signal, and the first signal is associated with at least an output current of a power converter. Additionally, the system includes a second comparator configured to receive a third signal and a fourth signal and generate a second comparison signal based on at least information associated with the third signal and the fourth signal. The third signal is related to the second signal, and the fourth signal is associated with a primary current flowing through a primary winding of the power converter. Moreover, the system includes a logic component configured to receive at least the second comparison signal and generate a logic signal based on at least information associated with the second comparison signal, and a pulse-width-modulation generator configured to receive at least the first comparison signal and the logic signal and generate a modulation signal based on at least information associated with the first comparison signal and the logic signal. The modulation signal is associated with a modulation frequency. Also, the system includes a driver component configured to receive the modulation signal and output a drive signal to a switch to adjust the primary current. Also, the system includes a first current generator configured to receive the modulation signal and output a compensation current based on at least information associated with the modulation frequency to generate a compensation voltage and adjust the first signal, and a second current generator configured to receive the modulation signal associated with the modulation frequency and output an offset current based on at least information associated with the modulation frequency to generate an offset voltage and adjust the fourth signal.

According to yet another embodiment, a method for regulating a power converter includes receiving a first signal and a second signal. The first signal is associated with at least an output current of a power converter. Additionally, the method includes processing information associated with the first signal and the second signal, generating a first comparison signal based on at least information associated with the first signal and the second signal, and receiving a third signal and a fourth signal, the third signal being related to the second signal. The fourth signal is associated with a primary current flowing through a primary winding of the power converter. Moreover, the method includes processing information associated with the third signal and the fourth signal, generating a second comparison signal based on at least information associated with the third signal and the fourth signal, receiving at least the second comparison signal, processing information associated with the second comparison signal, and generating a logic signal based on at least information associated with the second comparison signal. Also, the method includes receiving at least the first comparison signal and the logic signal, and generating a modulation signal based on at least information associated with the first comparison signal and the logic signal. The modulation signal is associated with a modulation frequency. Additionally, the method includes receiving the modulation signal, outputting a drive signal based on at least information associated with the modulation signal to adjust the primary current, outputting a compensation current based on at least information associated with the modulation frequency to generate a compensation voltage and adjust the first signal, and outputting an offset current based on at least information associated with the modulation frequency to generate an offset voltage and adjust the fourth signal.

Depending upon embodiment, one or more benefits may be achieved. These benefits and various additional objects, features and advantages of the present invention can be fully appreciated with reference to the detailed description and accompanying drawings that follow.

4. BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a simplified diagram showing a conventional flyback power conversion system with primary-side sensing and regulation.

FIG. 2 is a simplified diagram showing a conventional operation mechanism for the flyback power conversion system 100.

FIG. 3A and FIG. 3B are simplified diagrams showing switching frequency and peak current as functions of output current of a power conversion system in the constant-voltage (CV) mode according to an embodiment of the present invention.

FIG. 4 is a simplified diagram showing a power conversion system that adjusts switching frequency and peak current in response to output current according to an embodiment of the present invention.

FIG. 5 is a simplified timing diagram for the switch-mode power conversion system 400 with constant voltage control according to an embodiment of the present invention.

FIG. 6 is a simplified diagram showing a power conversion system that adjusts switching frequency and peak current in response to output current according to another embodiment of the present invention.

FIG. 7 is a simplified diagram showing a power conversion system that adjusts switching frequency and peak current in response to output current with voltage compensation according to yet another embodiment of the present invention.

FIG. 8 is a simplified diagram showing a compensation current generator for the power conversion system 700 according to an embodiment of the present invention.

FIG. 9 is a simplified diagram showing a power conversion system that adjusts switching frequency and peak current in response to output current with offset modulation current according to yet another embodiment of the present invention.

5. DETAILED DESCRIPTION OF THE INVENTION

The present invention is directed to integrated circuits. More particularly, the invention provides switching frequency and peak current adjustments in response to loading changes. Merely by way of example, the invention has been applied to a flyback power converter. But it would be recognized that the invention has a much broader range of applicability.

Referring to FIGS. 1 and 2, information about the output voltage of the power conversion system 100 often is sampled only once every switching period. The switching period is inversely proportional to the switching frequency, which usually is set low at no load or light load conditions to reduce power consumption. But the low switching frequency often leads to poor dynamic response for the power conversion system 100 if the load changes from no load or light load to full load. For example, if the switching frequency is several hundred Hz at no load or light load conditions, information about the output voltage of the power conversion system 100 is sampled once every several msec. If the load changes from no load or light load to full load (e.g., the output current changing to 1 A at full load), the output voltage may drop below an acceptable level, because the controller does not respond until the next sampling is performed after, for example, several msec. One way to solve this problem is to increase the switching frequency at no load or light load conditions. But if the switching frequency is increased, the peak current of the primary winding at no load or light load conditions should be limited such that the output voltage does not exceed an acceptable level.

FIG. 3A and FIG. 3B are simplified diagrams showing switching frequency and peak current as functions of output current of a power conversion system in the constant-voltage (CV) mode according to an embodiment of the present invention. These diagrams are merely examples, which should not unduly limit the scope of the claims. One of ordinary skill in the art would recognize many variations, alternatives, and modifications. The curve 310 represents the switching frequency (e.g., F_(sw)) as a function of output current (e.g., I_(out)), and the curve 320 represents the peak current (e.g., I_(peak)) for the primary winding as a function of output current (e.g., I_(out)). For example, if I_(out)=I₁, the power conversion system is at no load conditions, and if I_(out)=I₆, the power conversion system is at full load conditions. In another example, I₁<I₂<I₃<I₄<I₅<I₆.

As shown in FIG. 3A, the switching frequency (e.g., F_(sw)) changes with the output current (e.g., I_(out)) at a slope S_(1f) if I₁≦I_(out)<I₂, at a slope S_(2f) if I₂≦I_(out)<I₅, and at a slope S_(3f) if I₅≦I_(out)<I₆ according to one embodiment. For example, each of the slopes S_(1f), S_(2f), and S_(3f) is larger than zero.

As shown in FIG. 3B, the peak current (e.g., I_(peak)) for each switching period (e.g., T_(sw)) changes with the output current (e.g., I_(out)) at a slope S_(1p) if I₁≦I_(out)<I₃, at a slope S_(2p) if I₃≦I_(out)<I₄, and at a slope S_(3p) if I₄≦I_(out)<I₆ according to another embodiment. For example, the slopes S_(1p) and S_(3p) each are equal to or larger than zero. In another example, the slope S_(2p) is larger than zero. According to yet another embodiment, the power conversion system operates with pulse-frequency modulation for I₁≦I_(out)<I₃, with both pulse-frequency modulation and pulse-width modulation for I₃≦I_(out)<I₄, and with pulse-frequency modulation for I₄≦I_(out)<I₆. For example, the slopes S_(1p) and S_(3p) each are equal to zero, and the peak current (e.g., I_(peak)) increases from I_(min) to I_(max) at the slope S_(2p).

FIG. 4 is a simplified diagram showing a power conversion system that adjusts switching frequency and peak current in response to output current according to an embodiment of the present invention. This diagram is merely an example, which should not unduly limit the scope of the claims. One of ordinary skill in the art would recognize many variations, alternatives, and modifications.

The power conversion system 400 includes a primary winding 1410, a secondary winding 1412, an auxiliary winding 1414, a switch 1420 (e.g., a bipolar transistor), a current sensing resistor 1430, an equivalent resistor 1440 for an output cable, resistors 1450 and 1452, and a rectifying diode 1460. Additionally, the power conversion system 400 also includes a demagnetization detector 420, a sampling controller 422, a sampling switch 424, a capacitor 426, an oscillator 428, an error amplifier 430, an exponential generator 440, a comparator 450, a flip-flop component 452, a gate driver 454, comparators 460, 462, and 464, a logic component 466, resistors 470 and 472, and a capacitor 474.

For example, the primary winding 1410, the secondary winding 1412, the auxiliary winding 1414, the switch 1420, the current sensing resistor 1430, the equivalent resistor 1440, the resistors 1450 and 1452, and the rectifying diode 1460 are the same as the primary winding 110, the secondary winding 112, the auxiliary winding 114, the switch 120, the current sensing resistor 130, the equivalent resistor 140, the resistors 150 and 152, and the rectifying diode 160, respectively. In another example, the demagnetization detector 420, the sampling controller 422, the sampling switch 424, the capacitor 426, the oscillator 428, the error amplifier 430, the exponential generator 440, the comparator 450, the flip-flop component 452, the gate driver 454, the comparators 460, 462, and 464, the logic component 466, the resistors 470 and 472, and the capacitor 474 are located on a chip 410. In yet another example, the chip 410 includes terminals 412, 414, and 416.

FIG. 5 is a simplified timing diagram for the switch-mode power conversion system 400 with constant voltage control according to an embodiment of the present invention. This diagram is merely an example, which should not unduly limit the scope of the claims. One of ordinary skill in the art would recognize many variations, alternatives, and modifications.

As shown in FIG. 5, the waveform 510 represents turned-on and turned-off conditions of the switch 1420 as a function of time, the waveform 520 represents a ramping signal (e.g., V_(ramp)) as a function of time, the waveform 530 represents an amplified signal 431 (e.g., V_(ea)) as a function of time, and the waveform 540 represents a feedback signal 1455 as a function of time. Additionally, the waveform 550 represents a sensed signal 461 (e.g., V_(cs)) as a function of time, the waveform 552 represents a control signal 475 (e.g., V_(p)) as a function of time, and the waveform 554 represents a threshold signal 473 (e.g., V_(th) _(_) _(max)) as a function of time.

As shown in FIGS. 4 and 5, information about the output voltage is extracted through the auxiliary winding 1414 according to one embodiment. For example, the auxiliary winding 1414, together with the resistors 1450 and 1452, generates the feedback signal 1455 (e.g., V_(FB) corresponding to the waveform 540) at a node 1454. In another example, the feedback signal 1455 (e.g., V_(FB)) is received by at least the demagnetization detector 420 and the sampling switch 424.

In response, the demagnetization detector 420 outputs a signal 421 to the exponential generator 440 according to one embodiment. For example, the oscillator 428 also outputs a clock signal 429 to the exponential generator 440. In another example, the exponential generator 440 generates the ramping signal 441 (e.g., V_(ramp) corresponding to the waveform 520) as follows:

$\begin{matrix} {{V_{ramp}(n)} = {{\left( {V_{refb} - V_{refa}} \right) \times e^{- {(\frac{n \times T}{\tau})}}} + V_{refa}}} & \left( {{Equation}\mspace{14mu} 5} \right) \end{matrix}$

where V_(ramp) represents the voltage magnitude of the ramping signal 441. Additionally, V_(refa) and V_(refb) each represent a constant voltage level. For example, V_(refa) equals 1V, and V_(refb) equals 3V. Moreover, n represents the time for the ramping signal 441 to fall from V_(refb) since the last reset of the ramping signal 441 in terms of the number of the clock periods. T is the clock period of the clock signal 429. Furthermore, τ is the time constant. Specifically, if 0≦n≦64, τ=128×T; if 64<n≦128, τ=256×T; if 128<n≦256, τ=512×T; and if 256<n≦512, τ=1024×T.

In one embodiment, when the switch 1420 is turned off, the energy stored in the transformer is released to the output terminal. For example, the demagnetization process starts, and the current flowing through the secondary winding 1412 ramps down linearly. For example, when the demagnetization process almost ends and the current flowing through the secondary winding 1412 approaches zero, a sampling signal 423 is generated by the sampling controller 422 to sample the feedback signal 1455 (e.g., V_(FB) corresponding to the waveform 540) by closing the sampling switch 424. In another example, after the sampling process is completed, the sampling switch 424 is open in response to the sampling signal 423. In yet another example, the sampled voltage is held on the capacitor 426, and compared with a reference voltage V_(ref), such as 2V.

The difference between the sampled/held voltage and the reference voltage V_(ref) is amplified by the error amplifier 430 to generate the amplified signal 431 (e.g., V_(ea) correspond to the waveform 530) according to an embodiment. According to another embodiment, the amplified signal 431 is received by the resistor 470 and the negative input terminal of the comparator 450. For example, the resistor 470, together with the resistor 472 and the capacitor 474, outputs the control signal 475 (e.g., V_(p) corresponding to the waveform 552) to the comparator 460. In another example, the resistors 470 and 472 and the capacitor 474 form a compensation network, which perform attenuation and low-pass filtering to the amplified signal 431 and generates the control signal 475. In yet another example, the comparator 450 also receives the ramping signal 441 (e.g., V_(ramp) corresponding to the waveform 520) at the positive input terminal, and in response sends an output signal 451 to the flip-flop component 452.

As shown in FIG. 5, when the demagnetization process starts, the ramping signal 441 (e.g., V_(ramp) corresponding to the waveform 520) is restored to an initial value (e.g., V_(refb)), but after the demagnetization process is completed, the ramping signal 441 decreases exponentially according to one embodiment. In another embodiment, if the ramping signal 441 becomes smaller than the amplified signal 431 (e.g., V_(ea) corresponding to the waveform 530) in magnitude, the comparison signal 451 changes to the logic low level, causing the signal 453 to change to the logic high level and causing the switch 1420 to be turned on.

In another embodiment, a primary current 1411 that flows through the primary winding 1410 is sensed by the current sensing resistor 1430, which in response outputs the sensed signal 461 (e.g., V_(cs) corresponding to the waveform 550) to the comparators 460, 462, and 464. For example, if the switch 1420 is closed (e.g., being turned on), the transformer stores energy and the primary current 1411 ramps up linearly, causing the sensed signal 461 (e.g., V_(cs)) to also ramp up linearly. In another example, the positive terminal of the comparator 460 receives the control signal 475 (e.g., V_(p) corresponding to the waveform 552), and the negative terminal of the comparator 460 receives the sensed signal 461. In another example, the positive terminal of the comparator 462 receives the threshold signal 463 (e.g., V_(th) _(_) _(max) corresponding to the waveform 554), and the negative terminal of the comparator 462 receives the sensed signal 461. In yet another example, the positive terminal of the comparator 464 receives the sensed signal 461, and the negative terminal of the comparator 464 receives a threshold signal 465 (e.g., V_(th) _(_) _(min) which is smaller than V_(th) _(_) _(max) in magnitude).

In yet another embodiment, the comparators 460, 462, and 464 generate comparison signals 471, 473, and 479 respectively, all of which are received by the logic component 466. For example, the logic component 466 in response generates a logic signal 467.

According to one embodiment, the flip-flop component 452 receives the comparison signal 451 and the logic signal 467, and in response generates a signal 453. For example, as shown in FIG. 5, if the comparison signal 451 is at the logic low level but the logic signal 467 is at the logic high level, the signal 453 is at the logic high level, and if the comparison signal 451 is at the logic low level and the logic signal 467 is also at the logic low level, the signal 453 is at the logic low level. In another example, if the logic signal 467 is at the logic low level, the signal 453 from the Q terminal is also at the logic low level in order to turn off the switch 1420, regardless of whether the comparison signal 451 is at the logic high level or at the logic low level. In yet another example, if the logic signal 467 is at the logic high level and the comparison signal 451 is at the logic low level, the signal 453 is at the logic high level to turn on the switch 1420.

According to another embodiment, the signal 453 is received by the gate driver 454, which outputs a drive signal 455 to the switch 1420 through the terminal 412 (e.g., outputting the base current 455 to the bipolar transistor 1420 through the terminal 412). For example, if the signal 453 is at the logic high level, the drive signal 455 causes the switch 1420 to be closed (e.g., being turned on as shown by the waveform 510). In another example, if the signal 453 is at the logic low level, the drive signal 455 causes the switch 1420 to be open (e.g., being turned off as shown by the waveform 510).

As shown in FIGS. 4 and 5, the larger the output loading (e.g., the output current) is, the larger the amplified signal 431 (e.g., V_(ea) corresponding to the waveform 530) becomes, causing the off-time (e.g., T_(off)) of the switch 1420 to become shorter and the switching frequency (e.g., F_(sw)) to become higher according to one embodiment. According to another embodiment, the smaller the output loading (e.g., the output current) is, the smaller the amplified signal 431 (e.g., V_(ea) corresponding to the waveform 530) becomes, causing the off-time (e.g., T_(off)) of the switch 1420 to become longer and the switching frequency (e.g., F_(sw)) to become lower as shown in FIG. 3A.

According to yet another embodiment, the logic component 466 includes an OR gate and other components. For example, if the control signal 475 (e.g. V_(p)) is smaller than the threshold signal 465 (e.g., V_(th) _(_) _(min)) in magnitude, the peak magnitude of the sensed signal 461 (e.g., V_(cs) corresponding the waveform 550) is limited to the magnitude of the threshold signal 465 (e.g., V_(th) _(_) _(min) corresponding to the waveform 556), and the on-time of the switch 1420 (e.g., T_(on)) and the peak magnitude of the primary current 1411 remains constant regardless of the output loading (e.g., the output current) as shown for I₁≦I_(out)<I₃ in FIG. 3B.

In another example, if the control signal 475 (e.g., V_(p)) is larger than the threshold signal 465 (e.g., V_(th) _(_) _(min)) but smaller than the threshold signal 463 (e.g., V_(th) _(_) _(max)) in magnitude, the peak magnitude of the sensed signal 461 (e.g., V_(cs) corresponding the waveform 550) is limited to the magnitude of the control signal 475 (e.g., V_(p) corresponding to the waveform 552). For example, the control signal 475 (e.g., V_(p)) increases with the output loading (e.g., the output current) in magnitude; hence both the on-time of the switch 1420 (e.g., T_(on)) and the peak magnitude of the primary current 1411 increases with the output loading (e.g., the output current) as shown for I₃≦I_(out)<I₄ in FIG. 3B.

In yet another example, if the control signal 475 (e.g., V_(p)) becomes larger than the threshold signal 463 (e.g., V_(th) _(_) _(max)) in magnitude, the peak magnitude of the sensed signal 461 (e.g., V_(cs) corresponding the waveform 550) is limited to the magnitude of the threshold signal 463 (e.g., V_(th) _(_) _(max) corresponding to the waveform 554). For example, both the on-time of the switch 1420 (e.g., T_(on)) and the peak magnitude of the primary current 1411 remains constant regardless of the output loading (e.g., the output current) as shown for I₄≦out<I₆ in FIG. 3B.

As discussed above and further emphasized here, FIG. 4 is merely an example, which should not unduly limit the scope of the claims. One of ordinary skill in the art would recognize many variations, alternatives, and modifications. For example, the bipolar transistor 1420 is replaced by a MOS transistor as shown in FIG. 6.

FIG. 6 is a simplified diagram showing a power conversion system that adjusts switching frequency and peak current in response to output current according to another embodiment of the present invention. This diagram is merely an example, which should not unduly limit the scope of the claims. One of ordinary skill in the art would recognize many variations, alternatives, and modifications.

The power conversion system 600 includes a primary winding 1610, a secondary winding 1612, an auxiliary winding 1614, a switch 1620 (e.g., a MOS transistor), a current sensing resistor 1630, an equivalent resistor 1640 for an output cable, resistors 1650 and 1652, and a rectifying diode 1660. Additionally, the power conversion system 600 also includes a demagnetization detector 620, a sampling controller 622, a sampling switch 624, a capacitor 626, an oscillator 628, an error amplifier 630, an exponential generator 640, a comparator 650, a flip-flop component 652, a gate driver 654, comparators 660, 662, and 664, a logic component 666, resistors 670 and 672, and a capacitor 674.

For example, the primary winding 1610, the secondary winding 1612, the auxiliary winding 1614, the switch 1620, the current sensing resistor 1630, the equivalent resistor 1640, the resistors 1650 and 1652, and the rectifying diode 1660 are the same as the primary winding 110, the secondary winding 112, the auxiliary winding 114, the switch 120, the current sensing resistor 130, the equivalent resistor 140, the resistors 150 and 152, and the rectifying diode 160, respectively. In another example, the demagnetization detector 620, the sampling controller 622, the sampling switch 624, the capacitor 626, the oscillator 628, the error amplifier 630, the exponential generator 640, the comparator 650, the flip-flop component 652, the gate driver 654, the comparators 660, 662, and 664, the logic component 666, the resistors 670 and 672, and the capacitor 674 are located on a chip 610. In yet another example, the chip 610 includes terminals 612, 614, and 616.

In yet another example, the demagnetization detector 620, the sampling controller 622, the sampling switch 624, the capacitor 626, the oscillator 628, the error amplifier 630, the exponential generator 640, the comparator 650, the flip-flop component 652, the gate driver 654, the comparators 660, 662, and 664, the logic component 666, the resistors 670 and 672, and the capacitor 674 are similar to the demagnetization detector 420, the sampling controller 422, the sampling switch 424, the capacitor 426, the oscillator 428, the error amplifier 430, the exponential generator 440, the comparator 450, the flip-flop component 452, the gate driver 454, the comparators 460, 462, and 464, the logic component 466, the resistors 470 and 472, and the capacitor 474, respectively, except that certain modifications are made in order to drive a MOS transistor instead of a bipolar transistor. In yet another example, the auxiliary winding 1614, together with the resistors 1650 and 1652, generates a feedback signal 1655 at a node 1654.

FIG. 7 is a simplified diagram showing a power conversion system that adjusts switching frequency and peak current in response to output current with voltage compensation according to yet another embodiment of the present invention. This diagram is merely an example, which should not unduly limit the scope of the claims. One of ordinary skill in the art would recognize many variations, alternatives, and modifications.

The power conversion system 700 includes the primary winding 1410, the secondary winding 1412, the auxiliary winding 1414, the switch 1420 (e.g., a bipolar transistor), the current sensing resistor 1430, the equivalent resistor 1440 for the output cable, the resistors 1450 and 1452, and the rectifying diode 1460. Additionally, the power conversion system 700 also includes the demagnetization detector 420, the sampling controller 422, the sampling switch 424, the capacitor 426, the oscillator 428, the error amplifier 430, the exponential generator 440, the comparator 450, the flip-flop component 452, the gate driver 454, the comparators 460, 462, and 464, the logic component 466, the resistors 470 and 472, and the capacitor 474. Moreover, the power conversion system 700 also includes a frequency computation component 720, a frequency-to-current converter 730, and a current generation component 740.

For example, the demagnetization detector 420, the sampling controller 422, the sampling switch 424, the capacitor 426, the oscillator 428, the error amplifier 430, the exponential generator 440, the comparator 450, the flip-flop component 452, the gate driver 454, the comparators 460, 462, and 464, the logic component 466, the resistors 470 and 472, the capacitor 474, the frequency computation component 720, the frequency-to-current converter 730, and the current generation component 740 are located on a chip 710. In another example, the chip 710 includes terminals 712, 714, and 716. In yet another example, the frequency computation component 720, the frequency-to-current converter 730, and the current generation component 740 are parts of a compensation current generator.

According to one embodiment, the switching frequency increases with the output loading (e.g., the output current) and thus reflects the magnitude of the output loading (e.g., the magnitude of the output current) for at least I₂≦I_(out)<I₅ as shown in FIG. 3A. For example, the frequency computation component 720 receives the output signal of the flip-flop component 452, which is also received by the gate driver 454, and generates a frequency signal 721 that represents the magnitude of the switching frequency. In another example, the frequency signal 721 is received by the frequency-to-current converter 730 and is converted to a current signal 731. In yet another example, the current generation component 740 receives the current signal 731 and in response generates a compensation current 741 (e.g., I_(comp)). In yet another example, the current generation component 740 also includes a low-pass filter to smooth out the compensation current 741 (e.g., I_(comp)).

According to another embodiment, the compensation current 741 (e.g., I_(comp)) flows out of the chip 710 through the terminal 716, and generates a compensation voltage as follows:

$\begin{matrix} {V_{comp} = {\frac{R_{1} \times R_{2}}{R_{1} + R_{2}} \times I_{comp}}} & \left( {{Equation}\mspace{14mu} 6} \right) \end{matrix}$

where V_(comp) represents the compensation voltage, and I_(comp) represents the compensation current 741. Additionally, R₁ and R₂ represent resistance values of the resistors 1450 and 1452, respectively. For example, the compensation voltage is used to compensate for the voltage-drop due to the output cable (which is represented by the equivalent resistor 1440), and is also compensated for the output-voltage error due to cross regulation of the secondary winding and the auxiliary winding at no load and light load conditions. In another example, the compensation voltage is used to adjust the feedback signal 1455.

FIG. 8 is a simplified diagram showing a compensation current generator for the power conversion system 700 according to an embodiment of the present invention. This diagram is merely an example, which should not unduly limit the scope of the claims. One of ordinary skill in the art would recognize many variations, alternatives, and modifications.

The compensation current generator includes the comparators 1110 and 1112, the flip-flop component 1120, the signal generator 1130, the flip-flop components 1140, the encoding component 1150, the AND gate 1160, the switches 1170, the current sinks 1172, and the current source 1174. Additionally, the compensation current generator also includes transistors 1280, 1282, 1284, and 1286, a resistor 1290, and a capacitor 1292, an exponential generator 1010 and a frequency computation component 1014. U.S. patent application Ser. No. 12/859,138 is incorporated by reference herein for all purposes.

As shown in FIG. 8, the compensation current 741 that is dependent on the switching frequency is generated according to one embodiment. For example, since higher switching frequencies correspond to heavier loading conditions (e.g., larger output currents), and lower switching frequencies correspond to no load or light load conditions (e.g., smaller output currents); a larger compensation current is generated for lower switching frequency and a smaller compensation current is generated for higher switching frequency. In another example, the compensation current 741 is smoothed out by a low-pass filter that is formed by the resistor 1290 and the capacitor 1292. In yet another example, the compensation current 741 flows out of the chip 710 through the terminal 716, and together with the resistors 1450 and 1452 generates the compensation voltage (e.g., V_(comp)) that is superimposed with the feedback signal.

As discussed above and further emphasized here, FIG. 7 is merely an example, which should not unduly limit the scope of the claims. One of ordinary skill in the art would recognize many variations, alternatives, and modifications. For example, the bipolar transistor 1420 is replaced by a MOS transistor, and one or more components of the power conversion system 700 are modified in order to drive the MOS transistor instead of a bipolar transistor.

FIG. 9 is a simplified diagram showing a power conversion system that adjusts switching frequency and peak current in response to output current with offset modulation current according to yet another embodiment of the present invention. This diagram is merely an example, which should not unduly limit the scope of the claims. One of ordinary skill in the art would recognize many variations, alternatives, and modifications.

The power conversion system 900 includes a primary winding 1910, a secondary winding 1912, an auxiliary winding 1914, a switch 1920 (e.g., a bipolar transistor), a current sensing resistor 1930, an equivalent resistor 1940 for an output cable, resistors 1950 and 1952, and a rectifying diode 1960. Additionally, the power conversion system 900 also includes the demagnetization detector 920, the sampling controller 922, the sampling switch 924, the capacitor 926, the oscillator 928, the error amplifier 930, the exponential generator 940, the comparator 950, the flip-flop component 952, and the gate driver 954. Moreover, the power conversion system 900 also includes a frequency computation component 1720, a frequency-to-current converter 1730, and a current generation component 1740. Also, the power conversion system 900 includes a comparator 960, a frequency-to-current converter 1750, a current generation component 1760, and a resistor 1932.

For example, the primary winding 1910, the secondary winding 1912, the auxiliary winding 1914, the switch 1920, the current sensing resistor 1930, the equivalent resistor 1940, the resistors 1950 and 1952, and the rectifying diode 1960 are the same as the primary winding 110, the secondary winding 112, the auxiliary winding 114, the switch 120, the current sensing resistor 130, the equivalent resistor 140, the resistors 150 and 152, and the rectifying diode 160, respectively. In another example, the demagnetization detector 920, the sampling controller 922, the sampling switch 924, the capacitor 926, the oscillator 928, the error amplifier 930, the exponential generator 940, the comparator 950, the flip-flop component 952, the gate driver 954, the frequency computation component 1720, the frequency-to-current converter 1730, the current generation component 1740, the comparator 960, the frequency-to-current converter 1750, and the current generation component 1760 are located on a chip 910. In another example, the auxiliary winding 1914, together with the resistors 1950 and 1952, generates a feedback signal 1955 at a node 1954. In another example, the chip 910 includes terminals 912, 914, and 916.

In yet another example, the demagnetization detector 920, the sampling controller 922, the sampling switch 924, the capacitor 926, the oscillator 928, the error amplifier 930, the exponential generator 940, the comparator 950, the flip-flop component 952, the gate driver 954, the frequency computation component 1720, the frequency-to-current converter 1730, and the current generation component 1740 are substantially the same as the demagnetization detector 420, the sampling controller 422, the sampling switch 424, the capacitor 426, the oscillator 428, the error amplifier 430, the exponential generator 440, the comparator 450, the flip-flop component 452, the gate driver 454, the frequency computation component 720, the frequency-to-current converter 730, and the current generation component 740, respectively.

According to one embodiment, the switching frequency increases with the output loading (e.g., the output current) and thus reflects the magnitude of the output loading (e.g., the magnitude of the output current) in at least region II of FIG. 3A. For example, the frequency computation component 1720 receives the output signal of the flip-flop component 952, which is also received by the gate driver 954, and generates a frequency signal 1721 that represents the magnitude of the switching frequency. In another example, the frequency signal 1721 is received by the frequency-to-current converters 1730 and 1750 and is converted to current signals 1731 and 1751, respectively.

As shown in FIG. 9, the current generation component 1740 receives the current signal 1731 and in response generates a compensation current 1741 (e.g., I_(comp)), and the current generation component 1760 receives the current signal 1751 and in response generates an offset modulation current 1761 (e.g., I_(offset)) according to one embodiment. For example, the offset modulation current 1761 (e.g., I_(offset)) decreases with increasing switching frequency and thus also decreases with increasing output loading (e.g., with increasing output current).

According to another embodiment, the offset modulation current 1761 (e.g., I_(offset)) flows out of the chip 910 through the terminal 914, and generates an offset voltage as follows:

V _(offset) =R _(c) ×I _(offset)  (Equation 7)

where V_(offset) represents the offset voltage, and I_(offset) represents the offset modulation current 1761. Additionally, Re represents the resistance value of the resistor 1932.

For example, the offset voltage is used to adjust a sensed signal 963 (e.g., V_(cs)). In another example, using Equation 7, the peak magnitude of a primary current 1911 that flows through the primary winding 1912 is determined as follows:

$\begin{matrix} {I_{peak} = \frac{V_{th\_ OC} - {R_{c} \times I_{offset}}}{R_{s}}} & \left( {{Equation}\mspace{14mu} 8} \right) \end{matrix}$

where I_(peak) represents the peak magnitude of the primary current 1911, and V_(th) _(_) _(OC) represents the threshold signal 961. Additionally, R_(c) represents the resistance value of the resistor 1932. For example, the offset modulation current 1761 (e.g., I_(offset)) decreases with increasing output loading (e.g., with increasing output current); hence the peak magnitude of the primary current 1911 increases with increasing output loading (e.g., with increasing output current) but cannot exceed V_(th) _(_) _(OC)R_(s) according to Equation 8.

As shown in FIG. 9, the compensation current 1741 (e.g., I_(comp)) is generated by at least the frequency-to-current converter 1730 and the current generation component 1740, and the offset modulation current 1761 (e.g., I_(offset)) is generated by at least the frequency-to-current converter 1750 and the current generation component 1760 according to some embodiments. For example, the compensation current 1741 (e.g., I_(comp)) and the offset modulation current 1761 (e.g., I_(offset)) are different and separate, even though both the currents 1741 and 1761 are derived from the frequency signal 1721 that is generated by the frequency computation component 1720.

As discussed above and further emphasized here, FIG. 9 is merely an example, which should not unduly limit the scope of the claims. One of ordinary skill in the art would recognize many variations, alternatives, and modifications. For example, the bipolar transistor 1920 is replaced by a MOS transistor, and one or more components of the power conversion system 900 are modified in order to drive the MOS transistor instead of a bipolar transistor. In another example, the current generation components 1740 and 1760 each include a low-pass filter. In yet another example, the current generation components 1740 and 1760 share a low-pass filter that is used to smooth out both the compensation current 1741 (e.g., I_(comp)) and the offset modulation current 1761 (e.g., I_(offset)).

According to another embodiment, a system for regulating a power converter includes a comparator configured to receive a first signal and a second signal and generate a comparison signal based on at least information associated with the first signal and the second signal. The first signal is associated with at least an output current of a power converter. Additionally, the system includes a pulse-width-modulation generator configured to receive at least the comparison signal and generate a modulation signal based on at least information associated with the comparison signal, and a driver component configured to receive the modulation signal and output a drive signal to a switch to adjust a primary current flowing through a primary winding of the power converter. The modulation signal is associated with a modulation frequency corresponding to a modulation period. The modulation frequency increases with the output current at a first slope within a first current range, the modulation frequency increases with the output current at a second slope within a second current range, and the modulation frequency increases with the output current at a third slope within a third current range. The first current range and the third current range are separated by at least the second current range, and each of the first slope, the second slope, and the third slope is larger than zero. The primary current is associated with a peak magnitude for each modulation period. The peak magnitude remains constant or increases with respect to the output current at a fourth slope within a fourth current range, and the fourth slope is equal to or larger than zero. The peak magnitude increases with the output current at a fifth slope within a fifth current range, and the fifth slope is larger than zero. The peak magnitude remains constant or increases with respect to the output current at a sixth slope within a sixth current range, and the sixth slope is equal to or larger than zero. The fourth current range and the sixth current range are separated by at least the fifth current range. For example, the system is implemented according to FIG. 4, FIG. 6, FIG. 7, and/or FIG. 9.

According to another embodiment, a method for regulating a power converter includes receiving a first signal and a second signal. The first signal is associated with at least an output current of a power converter. Additionally, the method includes processing information associated with the first signal and the second signal, generating a comparison signal based on at least information associated with the first signal and the second signal, receiving at least the comparison signal, and generating a modulation signal based on at least information associated with the comparison signal. Moreover, the method includes receiving the modulation signal, and outputting a drive signal based on at least at least information associated with the modulation signal to adjust a primary current flowing through a primary winding of the power converter. The modulation signal is associated with a modulation frequency corresponding to a modulation period. The modulation frequency increases with the output current at a first slope within a first current range, the modulation frequency increases with the output current at a second slope within a second current range, and the modulation frequency increases with the output current at a third slope within a third current range. The first current range and the third current range are separated by at least the second current range, and each of the first slope, the second slope, and the third slope is larger than zero. The primary current is associated with a peak magnitude for each modulation period. The peak magnitude remains constant or increases with respect to the output current at a fourth slope within a fourth current range, and the fourth slope is equal to or larger than zero. The peak magnitude increases with the output current at a fifth slope within a fifth current range, and the fifth slope is larger than zero. The peak magnitude remains constant or increases with respect to the output current at a sixth slope within a sixth current range, and the sixth slope is equal to or larger than zero. The fourth current range and the sixth current range are separated by at least the fifth current range. For example, the method is implemented according to FIG. 4, FIG. 6, FIG. 7, and/or FIG. 9.

According to yet another embodiment, a system for regulating a power converter includes a first comparator configured to receive a first signal and a second signal and generate a first comparison signal based on at least information associated with the first signal and the second signal. The first signal is associated with at least an output current of a power converter. Additionally, the system includes a second comparator configured to receive a third signal and a fourth signal and generate a second comparison signal based on at least information associated with the third signal and the fourth signal. The third signal is related to the second signal, and the fourth signal is associated with a primary current flowing through a primary winding of the power converter. Moreover, the system includes a logic component configured to receive at least the second comparison signal and generate a logic signal based on at least information associated with the second comparison signal, a pulse-width-modulation generator configured to receive at least the first comparison signal and the logic signal and generate a modulation signal based on at least information associated with the first comparison signal and the logic signal, and a driver component configured to receive the modulation signal and output a drive signal to a switch to adjust the primary current. For example, the system is implemented according to FIG. 4, FIG. 6, and/or FIG. 7.

According to yet another embodiment, a method for regulating a power converter includes receiving a first signal and a second signal, and the first signal is associated with at least an output current of a power converter. Additionally, the method includes processing information associated with the first signal and the second signal, generating a first comparison signal based on at least information associated with the first signal and the second signal, and receiving a third signal and a fourth signal, the third signal being related to the second signal. The fourth signal is associated with a primary current flowing through a primary winding of the power converter. Moreover, the method includes processing information associated with the third signal and the fourth signal, generating a second comparison signal based on at least information associated with the third signal and the fourth signal, receiving at least the second comparison signal, processing information associated with the second comparison signal, and generating a logic signal based on at least information associated with the second comparison signal. Also, the method includes receiving at least the first comparison signal and the logic signal, generating a modulation signal based on at least information associated with the first comparison signal and the logic signal, receiving the modulation signal, and outputting a drive signal based on at least information associated with the modulation signal to adjust the primary current. For example, the method is implemented according to FIG. 4, FIG. 6, and/or FIG. 7.

According to yet another embodiment, a system for regulating a power converter includes a first comparator configured to receive a first signal and a second signal and generate a first comparison signal based on at least information associated with the first signal and the second signal, and the first signal is associated with at least an output current of a power converter. Additionally, the system includes a second comparator configured to receive a third signal and a fourth signal and generate a second comparison signal based on at least information associated with the third signal and the fourth signal. The third signal is related to the second signal, and the fourth signal is associated with a primary current flowing through a primary winding of the power converter. Moreover, the system includes a logic component configured to receive at least the second comparison signal and generate a logic signal based on at least information associated with the second comparison signal, and a pulse-width-modulation generator configured to receive at least the first comparison signal and the logic signal and generate a modulation signal based on at least information associated with the first comparison signal and the logic signal. The modulation signal is associated with a modulation frequency. Also, the system includes a driver component configured to receive the modulation signal and output a drive signal to a switch to adjust the primary current. Also, the system includes a first current generator configured to receive the modulation signal and output a compensation current based on at least information associated with the modulation frequency to generate a compensation voltage and adjust the first signal, and a second current generator configured to receive the modulation signal associated with the modulation frequency and output an offset current based on at least information associated with the modulation frequency to generate an offset voltage and adjust the fourth signal. For example, the system is implemented according to FIG. 9.

According to yet another embodiment, a method for regulating a power converter includes receiving a first signal and a second signal. The first signal is associated with at least an output current of a power converter. Additionally, the method includes processing information associated with the first signal and the second signal, generating a first comparison signal based on at least information associated with the first signal and the second signal, and receiving a third signal and a fourth signal, the third signal being related to the second signal. The fourth signal is associated with a primary current flowing through a primary winding of the power converter. Moreover, the method includes processing information associated with the third signal and the fourth signal, generating a second comparison signal based on at least information associated with the third signal and the fourth signal, receiving at least the second comparison signal, processing information associated with the second comparison signal, and generating a logic signal based on at least information associated with the second comparison signal. Also, the method includes receiving at least the first comparison signal and the logic signal, and generating a modulation signal based on at least information associated with the first comparison signal and the logic signal. The modulation signal is associated with a modulation frequency. Additionally, the method includes receiving the modulation signal, outputting a drive signal based on at least information associated with the modulation signal to adjust the primary current, outputting a compensation current based on at least information associated with the modulation frequency to generate a compensation voltage and adjust the first signal, and outputting an offset current based on at least information associated with the modulation frequency to generate an offset voltage and adjust the fourth signal. For example, the method is implemented according to FIG. 9.

For example, some or all components of various embodiments of the present invention each are, individually and/or in combination with at least another component, implemented using one or more software components, one or more hardware components, and/or one or more combinations of software and hardware components. In another example, some or all components of various embodiments of the present invention each are, individually and/or in combination with at least another component, implemented in one or more circuits, such as one or more analog circuits and/or one or more digital circuits. In yet another example, various embodiments and/or examples of the present invention can be combined.

Although specific embodiments of the present invention have been described, it will be understood by those of skill in the art that there are other embodiments that are equivalent to the described embodiments. Accordingly, it is to be understood that the invention is not to be limited by the specific illustrated embodiments, but only by the scope of the appended claims. 

1. A system for regulating a power converter, the system comprising: a comparator configured to receive a first signal and a second signal and generate a comparison signal based on at least information associated with the first signal and the second signal, the first signal being associated with at least an output current of a power converter; a pulse-width-modulation generator configured to receive at least the comparison signal and generate a modulation signal based on at least information associated with the comparison signal; and a driver component configured to receive the modulation signal and output a drive signal to a switch to adjust a primary current flowing through a primary winding of the power converter; wherein: the modulation signal is associated with a modulation frequency corresponding to a modulation period; the modulation frequency increases with the output current at a first slope within a first current range; the modulation frequency increases with the output current at a second slope within a second current range; the modulation frequency increases with the output current at a third slope within a third current range; the first current range and the third current range are separated by at least the second current range; and each of the first slope, the second slope, and the third slope is larger than zero; wherein: the primary current is associated with a peak magnitude for each modulation period; the peak magnitude remains constant or increases with respect to the output current at a fourth slope within a fourth current range, the fourth slope being equal to or larger than zero; the peak magnitude increases with the output current at a fifth slope within a fifth current range, the fifth slope being larger than zero; the peak magnitude remains constant or increases with respect to the output current at a sixth slope within a sixth current range, the sixth slope being equal to or larger than zero; and the fourth current range and the sixth current range are separated by at least the fifth current range.
 2. The system of claim 1 wherein the fourth slope is equal to zero.
 3. The system of claim 1 wherein the sixth slope is equal to zero.
 4. The system of claim 1 wherein: the peak magnitude remains constant at a first magnitude within the fourth current range; the peak magnitude remains constant at a second magnitude within the sixth current range; and the second magnitude is larger than the first magnitude.
 5. The system of claim 1 wherein: the first current range starts from a first current magnitude and ends at a second current magnitude; and the fourth current range starts from the first current magnitude and ends at a third current magnitude.
 6. The system of claim 5 wherein the second current magnitude is smaller than the third current magnitude.
 7. The system of claim 1 wherein: the third current range starts from a first current magnitude and ends at a second current magnitude; and the sixth current range starts from a third current magnitude and ends at the second current magnitude.
 8. The system of claim 7 wherein the first current magnitude is larger than the third current magnitude.
 9. A method for regulating a power converter, the method comprising: receiving a first signal and a second signal, the first signal being associated with at least an output current of a power converter; processing information associated with the first signal and the second signal; generating a comparison signal based on at least information associated with the first signal and the second signal; receiving at least the comparison signal; generating a modulation signal based on at least information associated with the comparison signal; receiving the modulation signal; and outputting a drive signal based on at least at least information associated with the modulation signal to adjust a primary current flowing through a primary winding of the power converter; wherein: the modulation signal is associated with a modulation frequency corresponding to a modulation period; the modulation frequency increases with the output current at a first slope within a first current range; the modulation frequency increases with the output current at a second slope within a second current range; the modulation frequency increases with the output current at a third slope within a third current range; the first current range and the third current range are separated by at least the second current range; and each of the first slope, the second slope, and the third slope is larger than zero; wherein: the primary current is associated with a peak magnitude for each modulation period; the peak magnitude remains constant or increases with respect to the output current at a fourth slope within a fourth current range, the fourth slope being equal to or larger than zero; the peak magnitude increases with the output current at a fifth slope within a fifth current range, the fifth slope being larger than zero; the peak magnitude remains constant or increases with respect to the output current at a sixth slope within a sixth current range, the sixth slope being equal to or larger than zero; and the fourth current range and the sixth current range are separated by at least the fifth current range.
 10. A system for regulating a power converter, the system comprising: a first comparator configured to receive a first signal and a second signal and generate a first comparison signal based on at least information associated with the first signal and the second signal, the first signal being associated with at least an output current of a power converter; a second comparator configured to receive a third signal and a fourth signal and generate a second comparison signal based on at least information associated with the third signal and the fourth signal, the third signal being related to the second signal, the fourth signal being associated with a primary current flowing through a primary winding of the power converter; a logic component configured to receive at least the second comparison signal and generate a logic signal based on at least information associated with the second comparison signal; a pulse-width-modulation generator configured to receive at least the first comparison signal and the logic signal and generate a modulation signal based on at least information associated with the first comparison signal and the logic signal; and a driver component configured to receive the modulation signal and output a drive signal to a switch to adjust the primary current.
 11. The system of claim 10 and further comprising: a first resistor including a first resistor terminal and a second resistor terminal; a second resistor including a third resistor terminal and a fourth resistor terminal; and a capacitor including a first capacitor terminal and a second capacitor terminal; wherein the second resistor terminal, the third resistor terminal, and the first capacitor terminal are coupled to each other; wherein: the first resistor is configured to receive the second signal at the first resistor terminal; and the second comparator is further configured to receive the third signal from at least the first capacitor terminal.
 12. The system of claim 10 and further comprising a compensation network configure to perform attenuation and low-pass filtering on the second signal and generate the third signal.
 13. The system of claim 10 and further comprising: a third comparator configured to receive the fourth signal and a first threshold signal and generate a third comparison signal based on at least information associated with the fourth signal and the first threshold signal; and a fourth comparator configured to receive the fourth signal and a second threshold signal and generate a fourth comparison signal based on at least information associated with the fourth signal and the second threshold signal; wherein the logic component is further configured to receive the third comparison signal and the fourth comparison signal and generate the logic signal based on at least information associated with the second comparison signal, the third comparison signal and the fourth comparison signal.
 14. The system of claim 10 wherein the logic component includes at least an OR gate.
 15. The system of claim 10 wherein the pulse-width-modulation generator includes at least a flip-flop component.
 16. The system of claim 10 wherein the switch is a bipolar transistor.
 17. The system of claim 10 wherein the switch is a MOS transistor.
 18. The system of claim 10 and further comprising a current generator configured to receive the modulation signal associated with a modulation frequency and output a compensation current based on at least information associated with the modulation frequency to generate a compensation voltage and adjust the first signal.
 19. The system of claim 18 wherein the current generator includes: a processing component configured to receive the modulation signal and generate a frequency signal representing the modulation frequency based on at least information associated with the modulation signal; a frequency-to-current converter configured to receive the frequency signal and generate a current signal based on at least information associated with the modulation frequency; and a current generation component configured to receive the current signal and output the compensation current based on at least information associated with the current signal. 20.-25. (canceled) 